Rules

Global rules

It is allowed to read anywhere from any memory page containing at least one byte of a ShortString, PChar, AnsiString or WideString string, including a #0 terminator.
It is not allowed to write past the end of AnsiStrings.
All functions must pass validation with range check on/off.
All functions must pass validation with overflow check on/off.
Functions are allowed to set compiler switches, but must reset them again.
A function can not rely on the FPU controlword or MXCSR register being default.
A function must leave the FPU controlword and the MXCSR register as it is at function entry.
Functions must behave exactly as the RTL functions do.
The rule above implies that functions must support non-nil-zero-length strings only if the RTL function does.
It is not allowed to use memory below the stack pointer.
Functions must not generate compiler warnings.

A function must allocate exactly enough space for a result string, but it is allowed to allocate extra bytes as long as the total size in dwords (including the #0 terminator) is the same

It is allowed to use the Rep Ret Instruction on all AMD targets. It is not allowed on all other targets.

RTL Replacement Target

It is allowed to read past the end of AnsiStrings and WideStrings including the dword containing the zero-terminator.
It is not allowed to read past the end of ShortStrings and PChar strings.

Target Descriptions

The following targets are currently active: Pentium 4, Pentium 3, Athlon XP, Athlon, Blended, Pascal, RTL replacement.

Pentium 4 Prescott

The fastest function that will run on all Pentium 4 Prescott is the winner of this category. All instruction sets supported by the Pentium 4 Prescott can be used, this includes: IA32, IA32 extensions, MMX, SSE, SSE2 and SSE3.

Pentium 4 Northwood

The fastest function that will run on all Pentium 4 Northwood and Willamette is the winner of this category. All instruction sets supported by the Pentium 4 Northwood and Willamette can be used, this includes: IA32, IA32 extensions, MMX, SSE and SSE2.

Pentium M Banias

Allowed instruction sets are: IA32, IA32 extensions, MMX, SSE and SSE2.

Pentium M Dothan

Allowed instruction sets are: IA32, IA32 extensions, MMX, SSE and SSE2.

Athlon XP

The fastest function that will run on all Athlon XP’s is the winner of this category. All instruction sets supported by the Athlon XP can be used, this includes: IA32, IA32 extensions, MMX, SSE, 3D-Now and 3D-Now+.

AMD 64

The fastest function that will run on all Opteron’s/FX51/XP64 is the winner of this category. All instruction sets supported by the Opteron can be used, this includes: IA32, IA32 extensions, MMX, SSE, SSE2, 3D-Now and 3D-Now+.

Blended

The winner is the fastest function that will run on Pentium 4 Prescott, Pentium 4 Northwood, Pentium M Dothan, Pentium M Banias, Pentium 3, Pentium 2, Athlon, Athlon XP and Opteron. Allowed instruction sets are: IA32, IA32 extensions and MMX. The minimum set of benchmark results used to calculate the winner are: 1 Pentium 4 Prescott, 1 Pentium 4 Northwood, 1 Pentium M Banias, 1 Pentium M Dothan, 1 Opteron and 1 Athlon XP.

Ideally many benchmark results should be included. This way we get an estimate of the blend of processors on the fast code interested marked.

RTL Replacement

Allowed instruction is: IA32.
Functions in this category must run on 486, Pentium, Pentium MMX, Pentium Pro, Pentium 2, Pentium 3, Pentium 4Northwood, Pentium 4 Prescott, Pentium M, AMD K6-2 and AMD K6-3, Athlon, Athlon XP, Opteron, Transmeta and Cyrix. This is the only target where code size matters. Each challenge will supply it’s own benchmark formula that adds a penalty for code size.
A minimum set of benchmark results must include one benchmark from 1 Pentium 4 Prescott, 1 Pentium 4 Northwood, 1 Pentium M Banias, 1 Pentium M Dothan, 1 Opteron and 1 Athlon

Pending Targets

AMD 64 with SSE3

Competition

A target winner gives 10 points.
A target entry gives 1 point.
Only one target entry per target gives points.

BASM